DDR6
DDR6 is the planned next generation of mainstream DRAM after DDR5, aimed at servers and the host CPUs that feed AI accelerators.
Text reviewed October 5, 2026
DDR6 is the planned next generation of mainstream DRAM after DDR5, aimed at servers and the host CPUs that feed AI accelerators.
Basic
DDR6 is the successor to DDR5 for mainstream DRAM. Used in server CPUs (Intel Granite Rapids-AP, AMD Turin, EPYC 10th gen) feeding GPU clusters. Not to be confused with HBM4 (the GPU-attached memory) · DDR6 is for CPUs.
Deep
DDR6 innovations: higher bus clock, increased burst length, on-die ECC default, and sub-channel architecture (two sub-channels per 64-bit channel) for better bandwidth utilization. Server DDR6 modules: RDIMM / LRDIMM / MCR-DIMM variants. Power-per-bit improved ~20% vs DDR5. CXL 3.0 integration allows DDR6 pools to attach to multiple CPUs.
Expert
DDR6 matters for AI mostly on the CPU side · host memory for training pipelines, model loading, data preprocessing. LLM training often constrained by CPU→GPU data pipeline bandwidth · faster DDR6 eases this. Chinese memory makers (CXMT) face sanctions-driven delays on DDR6; US + Korean + Japanese production dominates.
Depending on why you're here
- ·The next faster version of computer memory
- ·For regular computers that feed AI chips · different from AI chip memory
- ·Host-CPU memory for AI training pipelines
- ·Accelerates CPU→GPU data feed
- ·Memory cycle driver · Samsung, SK Hynix, Micron main winners
- ·Chinese CXMT sanctions push share to Korean/Japanese makers
- ·CXL 3.0 unlocks memory pooling economics
- ·Sub-channel architecture · on-die ECC
DDR6 is the CPU-side memory upgrade AI training waits on · faster host memory unlocks data-pipeline bottlenecks.