Every Memory · Tracked
Every memory generation powering AI chips and beyond. HBM bandwidth, supplier market share, cross-industry demand pressure, and pricing trends · sourced from earnings calls, JEDEC specs, and industry forecasts.
- AI absorption88%
- Supply-demand gap50/100
- Supplier concentration40/100
- Pricing pressure39/100
- Cross-industry strain45/100
- AI demand dominanceAI absorbs 88% of all HBM output
- Supply-demand gapDemand exceeds supply by ~25%
- Supplier concentrationSK hynix holds 53% HBM market share
- Extended lead times52-week wait for new HBM orders
HBM generation ladder
Each generation roughly doubles bandwidth · the engine of AI scaling
Next-generation HBM doubling interface width to 2048-bit. Enables 1.74 TB/s per stack. Targeted at NVIDIA Rubin and AMD next-gen. SK hynix sampling to customers, Samsung and Micron in development. First volume expected late 2026.
The dominant HBM generation for 2024-2026 AI training. Enhanced version of HBM3 with higher per-pin data rate (9.6 Gbps). Powers NVIDIA B200, GB200, GB300, AMD MI325X/MI355X, and hyperscaler ASICs. SK hynix leads production, Samsung struggling with yields, Micron validated for NVIDIA.
First JEDEC HBM3 generation with 1024-bit interface. Powers NVIDIA H100 and H200, AMD MI300X, Google TPU v5e, AWS Trainium. SK hynix was sole initial supplier for H100. Mature production with stable supply as demand shifts to HBM3e.
Enhanced HBM2 used in NVIDIA A100, Google TPU v4, Intel Gaudi 2, and various HPC accelerators. Mature technology with declining demand as the industry transitions to HBM3/3e. Still in production for legacy deployments.
Cross-industry demand
Memory is not just AI · every industry competes for the same DRAM fabs
HBM is ~30% of total DRAM revenue but growing at 78% YoY. AI absorbs 88% of all HBM output. Demand exceeds supply by ~25%, with 52-week lead times for new orders.
Training and inference clusters. Each NVIDIA B200 requires 192 GB HBM3e. A single DGX B200 rack needs 1.5 TB of HBM plus 4 TB of DDR5 host memory.
Every server refresh cycle is DDR4 → DDR5. AWS, Azure, GCP collectively adding millions of DDR5 DIMMs per quarter. AI inference servers need 512 GB to 2 TB of DDR5 host memory.
AI PCs require 32 GB+ LPDDR5X (up from 8 GB standard). AI phones need 12-16 GB. Gaming GPUs shifting to GDDR7. The on-device AI trend is a memory demand multiplier.
ADAS, autonomous driving, and in-vehicle infotainment. Tesla FSD computer uses LPDDR5. Each autonomous vehicle needs 32-128 GB of memory. The automotive memory TAM is growing faster than consumer.
5G infrastructure, switching ASICs (Broadcom, Marvell), and edge compute. High-bandwidth switching chips increasingly use HBM for packet buffers.
Robotics, factory automation, medical imaging, defense systems. Growing but fragmented demand.
Supplier landscape
4 memory suppliers · HBM + DRAM market share
The world's leading HBM manufacturer. SK hynix was first to ship HBM3 for NVIDIA's H100 and leads HBM3e volume production. Their dominance in HBM is driven by superior stacking yields and early NVIDIA qualification. Also a major DDR5 and LPDDR5X supplier.
The world's largest DRAM manufacturer by total revenue but struggling in HBM. Samsung dominates DDR5 and LPDDR5X (Apple's primary supplier) but trails SK hynix in HBM3e yields. Their HBM4 program is critical for regaining competitive parity. Also operates the only foundry-DRAM vertical integration.
The only US-headquartered DRAM manufacturer. Micron's HBM3e was validated by NVIDIA for Blackwell, a major breakthrough. Their GDDR6X near-monopoly (PAM4 pioneer) gave them pricing power. CHIPS Act recipient building new fabs in Idaho and New York. Strategic importance for US semiconductor sovereignty.
China's leading DRAM manufacturer, founded as part of the national semiconductor self-sufficiency push. Currently producing DDR4 and ramping DDR5 with limited export due to US export controls on advanced DRAM equipment. Cannot produce HBM without EUV lithography access. Strategically important for China's domestic market but not a factor in the global AI memory supply chain.
Pricing trends
Per-GB ASP · YoY change · trend direction
| Generation | Category | $/GB | YoY |
|---|---|---|---|
| HBM4Development SH S M | HBM | n/a | n/a |
| GDDR7Ramping S SH M | GDDR | $8 | n/a |
| HBM3eVolume SH S M | HBM | $25 | +45% |
| HBM3Volume SH S M | HBM | $16 | -8% |
| LPDDR5XVolume S SH M | LPDDR | $3.5 | +12% |
| DDR5Volume S SH M C | DDR | $2.8 | +18% |
| HBM2eMature S SH M | HBM | $8.5 | -22% |
| GDDR6XVolume M S | GDDR | $5.5 | -10% |
All generations
8 memory types · HBM + DDR + LPDDR + GDDR
Next-generation HBM doubling interface width to 2048-bit. Enables 1.74 TB/s per stack. Targeted at NVIDIA Rubin and AMD next-gen. SK hynix s...
Next-generation graphics memory using PAM3 signaling for 36 Gbps per pin. Targeted at NVIDIA RTX 50-series and AMD RDNA 4 consumer GPUs. Als...
The dominant HBM generation for 2024-2026 AI training. Enhanced version of HBM3 with higher per-pin data rate (9.6 Gbps). Powers NVIDIA B200...
First JEDEC HBM3 generation with 1024-bit interface. Powers NVIDIA H100 and H200, AMD MI300X, Google TPU v5e, AWS Trainium. SK hynix was sol...
Low-power memory standard driving the on-device AI revolution. Powers Apple M-series, Qualcomm Snapdragon X, and Samsung Galaxy AI. Critical...
Standard DRAM for servers, workstations, and high-end consumer PCs. DDR5-5600 to DDR5-8400 speeds. Critical for AI inference servers where G...
Enhanced HBM2 used in NVIDIA A100, Google TPU v4, Intel Gaudi 2, and various HPC accelerators. Mature technology with declining demand as th...
PAM4-signaling graphics memory powering NVIDIA RTX 30/40-series consumer GPUs. Micron exclusive until recently. Still the workhorse of consu...
Frequently asked
Data as of April 14, 2026 · every change kept
Why is HBM so important for AI?
High Bandwidth Memory (HBM) stacks DRAM dies vertically and links them with through-silicon vias (TSVs), which gives far more bandwidth per package than standard DDR memory. 18 of the 20 AI chips tracked on BenchGecko use HBM. Without it, large model training and inference would be limited by memory bandwidth.
Who makes HBM and why is it scarce?
HBM suppliers in the dataset: SK hynix 53%, Samsung 30% and Micron 17%. SK hynix leads with 53% of HBM supply. The dataset puts HBM demand growth at 78% year over year, a supply gap of about 25% and lead times near 52 weeks for new orders, as of Apr 14, 2026. Adding HBM capacity takes time and specialized packaging equipment.
What is the difference between HBM3, HBM3e, and HBM4?
HBM3 (2022): 819 GB/s per stack, 1024-bit interface · HBM3e (2024): 1,180 GB/s per stack, 1024-bit interface · HBM4 (2026): 1,740 GB/s per stack, 2048-bit interface. Each generation raises bandwidth per stack, which is what lets new accelerators feed larger models.
How does memory affect AI chip pricing?
HBM is one of the largest cost components of an AI accelerator. In the dataset, HBM3e sells for about $25 per GB (+45% year over year) versus about $2.8 per GB for DDR5, as of Apr 14, 2026. When HBM prices rise, GPU prices and cloud compute costs follow.
Why does memory demand affect industries beyond AI?
All memory types share DRAM fabrication capacity. When fabs shift production to high-margin HBM, less capacity is left for DDR5 in servers and LPDDR5X in phones and laptops, so AI demand also raises memory costs for cars, smartphones and cloud servers. The dataset sizes the DRAM market at $96.4B, as of Apr 14, 2026.
What is CoWoS and how does it relate to memory?
CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's advanced packaging technology that physically bonds HBM stacks to the GPU die on a silicon interposer. Even when HBM supply is sufficient, the CoWoS packaging step is often the bottleneck. The GPU die and HBM stacks are manufactured separately, then combined in the CoWoS process. CoWoS capacity, not HBM production, sometimes becomes the binding constraint.
See also
Keep exploring the compute graph