Every Foundry · Tracked

TSMC fabricates 90% of the AI chips tracked by BenchGecko, including B200, GB200, TPU v7, Trainium2 and GB300. Leading-edge nodes and CoWoS packaging capacity are why most flagship accelerators are built there.

CoWoS (Chip-on-Wafer-on-Substrate) is TSMC's advanced packaging technology that connects GPU dies to HBM stacks on a silicon interposer. For AI accelerators, packaging capacity rather than wafer output is often the binding constraint: a finished die is useless until it is packaged with its HBM. Packaging utilization per foundry is shown in the capacity section.

Yes, at a cost. SMIC reached a 7nm-class node with DUV multi-patterning, which needs more lithography steps, gives lower yields and costs more per wafer. Chips in the dataset made this way: Ascend 910C. Without EUV access, further shrinks get harder and more expensive.

Intel 18A is Intel Foundry's 1.8nm-class node, with RibbonFET gate-all-around transistors and PowerVia backside power delivery. It matters because it is the main US-based leading-edge alternative to TSMC for outside customers. Status in the dataset: risk (2025).

BenchGecko tracks 22 fab locations across 9 countries. Fab geography matters for supply chain resilience, export controls and datacenter proximity.

Capacity utilization is the share of a foundry's production capacity in use. Above about 95%, a foundry is effectively full and new orders face long lead times. Across tracked foundries, advanced nodes averaged 72% utilization in the latest reported quarter (2025-Q1), and at least one foundry reports packaging at 95% or more. Figures come from quarterly earnings disclosures, as of Apr 14, 2026.