MTIA v2
MTIA v2 is a Meta custom AI chip (ASIC) based on the PE grid + SRAM architecture, first released in 2024.
Built from BenchGecko data as of April 14, 2026 · updates when the data changes
MTIA v2 is a Meta custom AI chip (ASIC) based on the PE grid + SRAM architecture, first released in 2024.
Basic
The Meta Training and Inference Accelerator v2 is a custom AI chip (ASIC) made by Meta, codenamed Artemis. Peak throughput is 354 TFLOPS at FP16/BF16 and 708 TFLOPS at FP8. It carries 128 GB of HBM3 with 1.6 TB/s of memory bandwidth. Rated power (TDP) is 90 W. It is built on N5 at TSMC.
Deep
In the BenchGecko dataset it sits in the specialized tier: wafer-scale, LPU and other custom designs. Disclosed buyers include Meta. Specs come from manufacturer datasheets; the spec card on this page shows the dataset values and their as-of date.
Expert
That is 3.93 FP16 TFLOPS per watt. Memory bandwidth per unit of compute is 4.52 GB/s per FP16 TFLOP: a higher ratio helps memory-bound inference, while peak TFLOPS matter more for compute-bound training. Fabrication: Taiwan. Real throughput depends on the model, precision, batch size and software stack, so compare tokens per second per dollar for your own workload.
Depending on why you're here
- ·MTIA v2: 354 TFLOPS FP16/BF16 · 708 TFLOPS FP8
- ·Process: N5 at TSMC
- ·Tier: specialized
- ·128 GB of HBM3 per chip
- ·No public cloud listing for MTIA v2 in the dataset
- ·Compare it with other chips on /hardware/mtia-v2
- ·Disclosed buyers: Meta
- ·Meta · fabbed at TSMC
- ·Supply tightness is tracked on /hardware
- ·MTIA v2 is a chip built to run AI, made by Meta
- ·It has 128 GB of fast memory so large models fit
- ·Companies buy or rent these to train and serve AI models
Frequently Asked Questions
Read the primary sources
- MTIA v2 blogai.meta.com